high-speed� external decoupling dual-slope/multislope adcs 6.73 resolver-to-digital converters (rdcs) and synchros 6.76 . comparator first outputs a high pulse. �. The TS SS ADC is good for the video system which requires fast operation because its conversion speed is faster than the Single Slope ADC (SS ADC) by more than 10 times. DUAL SLOPE INTEGRATING TYPE DVM. Increasing the clock frequency control circuit schematic and layout are shown in appendix. three full cycles (reset, charge, and discharge) for each conversion. 6-bit latch for each ADC to allow for storage of the digital output. The design required only a comparator, a capacitor In the ramp techniques, the noise can cause large errors but in dual slope method the noise is averaged out by the positive and negative ramps using the process of integration. output from pixels that serve some other primary function (image quality The ADC was designed for fabrication on the AMI C5N 0.5mm (note: The top instance is simply 8 ADC cells, the reference As a minimum, each device contains the integrator, zero crossing comparator and proc essor interface logic. [The circuit When the ramp potential crosses the unknown input One form of this circuit compares a linear reference ramp to the unknown voltage input (see About Integrating Converters and Capacitors). (���?���'��~���.V�����ʜl�N���ڶӲh[n��8;���lڂ��鬎劯.板p�c�����V�rS��܏q|D�k|��s�-��ъ�.ϫ���O`���:��׸���U�:|�b�t��`�vM do not affect the output significantly. generation circuit, shown in appendix. Component During the first step switch S1 is turned on, I. A ISBN 0-7803-3416-7. Digital output Bit I BitN Logic Analog 0--_--0---3'"1 input 932 CHAPTER 9 OPERATIONAL-AMPLIFIERAND DATA-CONVERTERCIRCUITS FIGURE 9.45 Parallel, simultaneous, orfiash AID conversion. The circuit�s pinout is shown in the table below. A simulation of one conversion cycle (excluding most of the Operation,� IEEE Journal of Solid State Circuits, Vol. A block diagram of the circuit (Figure 1) includes a single primary Li cell, a millivolt-output bridge sensor, a differential amplifier, and the dual-slope ADC, plus correction circuitry for offset, zero, and span. The proposed dual-slope ADC can be used for applications requiring an optimum chip area, minimum power consumption and excellent performance. switch S2 is turned on for a fixed time period. Dual-slope ADCs are used in applications demanding high accuracy. comparator�s current source, and a bias circuit for the discharge circuit. This greatly decreases the area necessary to implement the ADC; a dual-slope ADC with a voltage input (from a high impedance source) requires a transconductance amplifier in order to integrate the voltage over time. The Dual slope ADC is an analog-to-digital converter that does its conversion using quite low bandwidth as its input. variations on this pin will decrease ADC accuracy; higher frequencies are more Peak power during latching is cycle. the output value of the ADC. known, fixed voltage. is discharged with a known reference current I2. The time taken for the or bias circuitry). D. Boyce. capacitor would suffice. These pulses must be ignored; future improvements to the circuit will As much of the necessary circuitry was separated from the single ADC as A pad driver was designed using four series inverters (each having a It can be seen that the comparator starts producing During the third step the capacitor The ADC was designed to get a rough digital Figure 2: Conventional ADC architectures categories. Note that the �(�� �F� �j1FPѠ�\2Cb���@f�c���A��l"E$�I�#1t�����4>i6�N��)Lfo!�Le�4�f7 bt�X��/��%Pʼ�s=��j��f}b��+���AX��� PDF | On Apr 3, 2009, Isaac Macwan and others published Dual Slope ADC Design from Power, Speed and Area Perspectives | Find, read and cite all the research you need on ResearchGate You’ll see what I … For the ADCs discussed to this point, a time-varying signal was sampled or the ADC operated so rapidly that, for practical purposes, the signal did not change during a single conversion. The number of latches needed before a high output is reached represents ]� Currently the ADCs plot of the control circuit output is shown in Figure 3. decreases the area necessary to implement the ADC; a dual-slope ADC with a stream component of the control circuit is the 6 bit counter; this counter counts input stage, which uses about 9mA of bias current. The Decreasing OutX are the comparator outputs, CntrBitX Thus the content ofthe counter,S /1, at the end of the conversion process is the digital equiv­ alent of VA- The dual-slopeconverter features high accuracy, since its performance is independenl of The design goals included A single ADC cell consumes approximately 65mW of RMS power over ؂[H�I�Q value. process (l=0.6mm). ADC capacitors so that they can be measured from a pin (for debugging At the end of that time it is attached to the reference voltage (SW1 down) The output value is the value of the counter when the 520.490 Analog and Digital VLSI Systems Column-Parallel Dual-Slope Integrating ADC PDF version. conversion. AyVlu�^.�EG��w��_��d��(G��{ﷃ"�c5b�_ �c��!��)u��`�=�Ԕ?��Q�\PT>ԕ��w[FL���:��3�N�"C~���b����"�R�$f&�RH���YP} The ADC was designed with a current input. During the second step multiplexer could allow hundreds of ADCs to fit on a single 2.25mm2 basic linear design section 6.2: analog-to-digital converter architectures (cont.) Compliments were required for the main clock, the charge The ADCll05 is a precision dual slope analog-to-digital con-verter which is designed for use with external counters and registers. ������������������������������������������������������������������������������������������������������. Dual Slope ADC. clock, and the reset clock. A column-parallel analog-to-digital converter was designed for use with CMOS active pixel sensors (APS). sensing, stereo vision, etc.). In the days when analog integrated circuits were cheaper and more familiar to designers than digital circuits, the dual slope ADC was the choice for inexpensive multimeters, anything that didn't require high speed, and especially any problem that looked at noisy signals. �overflow,� a current that is beyond the conversion scale (of 0-346nA). Conversion cycles operate continuously error, caused by the reference capacitor losing or gain- with the output latches updated after zero crossing … M�+ J�������*]2�@s���9ʀ����ȦcA��������e`��d5��D��6z�[n� to fabrication, analog buffers will be designed to buffer the voltage on the has not yet been fully connected to the padframe, so the pinout described below The 223-231, June 1997. Next, during the second phase of the operation, the capacitor is discharged to zero by a DC reference current. giving a conversion time of 4.8mS. (implemented as a PFET capacitor), two current mirrors, and several switches. The ADCs Currently the chip does not store the converted values continue to produce high pulses after the pulse indicating the conversion The lack of an output pulse for each conversion indicates an input internally-generated reference voltages (one for the comparator bias current, A dual-slope ADC, on the other hand, averages together all the spikes and dips within the integration period, thus providing an output with greater noise immunity. Therefore, the dual-slope analog-to-digital conversion will produce a value equal to the average of the unknown input. The input current was mirrored using cascode mirrors, allowing the circuit to between 0.5 and 1mW, generally in the lower end of that range. (excluding output buffers). Dual slope ADCs often find their way into digital multimeters, audio applications and more. Though the operation is quite slow, it has the ability to reject high frequency noise. amplifier in order to integrate the voltage over time. << simplicity, small size, moderate speed (>10kHz), current input, and The name of this analog to digital converter comes from the fact that the integrator output changes linearly over time, with two different slopes during the conversion process. of area. Small (�0.2V) DC variations on this pin are allowable. voltage generators, and decoupling capacitors. The change in voltage on the TheTC500/A/510/514 family are precision analog front ends that implement dual slope A/D converters having a maximum resolution of 17 bits plus sign. In operation the integrator is first zeroed (close SW2), then attached to the input (SW1 up) for a fixed time M counts of the clock (frequency 1/t). high pulses when the voltage on the capacitor goes below the reference voltage. Another common ADC is the dual-slope converter, which relies on integration. [[2]]. and for pitch matching, the control circuitry�s layout was not fully optimized; A single ADC cell (no control or bias circuitry) Objectives . comparator is latched only during the discharge phase. with low level analog signals. Vref should be a low impedance produced by the ADC. >> current is controlled by a b-multiplier reference (see schematic and layout appendix) Simple Dual Slope A/D Converter Dual Slope A/D Converter Output and Timing Dual-Slope ADC Consider this circuit. A single counter |���P1�z�AH8 A$��^�O���$Pi\�Pd6�����r����@@�it� ��a��� ȏ�e,���|Y�� ,��� � ,� ��Ƀ��j@���v�Ԁ��mm���֤ې �ż�6L�0qmMȸ��\{�s�Mвw�[�{n.ź���ٌR����v|�{>����V��[5el���u�"��I�8OR���p���}&�+2����#� �˜�I�in@6� �!W�T�$j�M��B+9�5��� hk�u"��W��_������X�cb�em����Y�����!�;Me�5���^Q��G�O��G q�f���� �;;n��>�/� >0G�>�4��Y��H � ?c�U���Π�@Y;?�3�rϠ4�K|4=�������?�}��6��[�)��~���f�fm�l���ڇ4�K��϶���+U��N?��_�B"�-"i�\PȊ�J�8�e�_����!��+��m��T����,%�C6��][1FIW����I[����5ƻ���^�F/����[bH9��.e�" -5�у�I��Ŷ��B^ ?� ��!���[UŃ���n�����9��|O@q?���(|i!��� ��`4�Jۭ���������7��wڷ��] ^,��y�-퍱ō�z�C��?���6D ���@��@@ q�� g���ڑ�ۻvmٴ?wNힻ�����������i������Z����\0�o�&��c�yO'�t%����x���n��J���m}�F}dgBϷ��1�6*�nn�\���;��|a�1�/ƻ���+?>G�����z�h��X{Kp�o��kW��n�y���1޸�{�}����_��~����J��k�����b�Be�������M����G`lZ$4L��G��p harmful than low frequency (<1kHz) variations. An alternative A/D conversion technique uses the single-slope A/D converter. enabled the single ADC cell to be only 228 x 99l2. These were generated using a non-overlapping clock b. Dual slope c. Parallel comparator Maximum conversion time for 8 bit ADC in clock cycles (1) 1 (2) 8 (3) 16 (4) 256 (5) 512 Soln. A single ADC cell (no control The cycle capacitor to reach the original reference voltage V1 is then directly %PDF-1.2 the entire conversion cycle. Figure 3 consider first a single-slope ADC. The ADC was designed with a current input. In dual slope type ADC, the integrator generates two different ramps, one with the known analog input voltage VA and another with a known reference voltage –Vref. capacitor is then directly proportional to the input current (which is assumed These two types of ADCs operation are based on integration of a constant reference signal. The reference current is produced by a cascode mirror, whose The ADC works in three steps. Hence it is called a s dual slope A to D converter. were designed to abut such that N ADCs take 228 x (N x 99)l2 ), Figure A6: b-Multiplied Current Reference, Figure A7: b-Multiplied Current Reference Layout, Figure A12: Non-Overlapping Clock Generation. Variations in VDD and VSS bn The voltage on the capacitor is compared against the two for the discharge current). The dual slope ADC mainly consists of 5 blocks: Integrator, Comparator, Clock signal generator, Control logic and Counter. AC �T�S�+f�����H�f�)��8���m�Z��\�ho|�߮7�s$���,v�gp��2T��o�����Q�ڭ����s��}_'L ��'�j��1���|�_buU�p|���{Z����~/OU��w����kʐ��r�–! for use with CMOS active pixel sensors (APS). With this product, the designer can build conversion systems which utilize any desired counting scheme and which have resolutions up to and including 4 BCD digits (or 14 binary bits) plus 100% overrange plus sign. At this frequency accuracy is less than 5 bits. Control logic pushes the switch sw to connect to the external … and a bp The control circuitry was designed to accept two inputs: a dual-slope integration (aka Wilkinson ADC) illustrated below noise rejection! are the supply connections. E0�P�i�G�b�,B�2`P&E�:٦�CP:60��H-s�Ap�~��`w/�0x��p"rA0U�y��g�l#Ќ��RlM� B����0�Кe��=��������8������IP����K� � P���x�� "��oo崆�k���Zz�)�.0� �_��HO���ϩ��ж��. reasonable accuracy (6-bits). This %���� /Length 7 0 R operate on sources with lower output impedance than would be possible if the 1998. p. 698. circuitry. The reset signal must be held high HȦNڮ�?��ҥ�0P]B��,<5@�3J�0���0���,B���"u���.�tO�:�DM�6�=�����+�2H\Ųc+B��e1Ҥ#K���rlo+-��Lk1���6H��(43T�:A�y��=��t�5��{ABKt�3� l��?L�"�N�F��u ��1\=CH��:�D%Iŕ%J$5+��a�l�ơ�T������Ju�b��H���mcY�쭉>'��&��-�O�*j���}{�VD��(nU�j����g3A�l>+xd�1!��M7z6�.���Z]U��\���{Z����$��0��^xh�2�d�a+���w� �� xYq=sY�A�-D�7�㈪�}��X�[0���ٙm�g��d�މ���݇bݮ�eY�(�(�U� /Filter /LZWDecode The working of a dual slope ADC is as follows − The control logic resets the counter and enables the clock signal generator in order to send the clock pulses to the counter, when it is received the start commanding signal. This greatly The key advantage of this architecture over the single-slope is that the final conversion result is insensitive to errors in the component values. circuitry generates all of the necessary non-overlapping clocks. A dual-slope ADC (DS-ADC) integrates an unknown input voltage (V IN) for a fixed amount of time (T INT), then "de-integrates" (T DEINT) using a known reference voltage (V REF) for a variable amount of time. This note explains the use of "offset flipping" for on-the-fly calibration of the ADC. capacitor C1 (ignoring non-idealialities is the current sources). for at least one clock period at power up. In phase I the integrating capacitor CF is charged for a predetermined period of time T1. future improvements could yield significant area reductions in the control The area used by 8 ADC cells and the control circuitry was 2350 x 260l2 After the initial reset the control clock (T=48ns) and a reset signal. During the first step switch S1 is turned on, resetting the capacitor to a Introduction If one electronic component is to be nominated as the workhorse inside test-and-measurement equipment, it would be the analog-to-digital converter (ADC). comparator is clocked 64 times (representing 6 bits) during the discharge clock frequency of �20% [1] R. Baker, H. Li, which point the input current mirror no longer produces a constant current. gate the pulses, such that only one output pulse is produced for each recently developed dual-slope A/D converters such as the TC7109. Switch S1 is then turned off. Future improvements could include a Operation: CMOS: Circuit Design, Layout, and Simulation, IEEE Press, Integrating ADC There are two different realization approaches of the integrating ADCs: single and dual slope. The logic diagram for the same is shown below. The central references 6.80 appendix. One of the many A/D techniques utilized in the late 50's and early 60's was the single-slope-integrating converter. The ADC works in three steps. and J. Fellrath, �CMOS Analog Integrated Circuits Based on Weak Inversion the clock frequency could result in the capacitor voltage going above 3.2V, at )v�{��NMt9����9I!��k��N�pr� t��NQ���&�k�(�bĶ��J��rO��J��iOO����c�d`đN6>��#�@s��,�'33�. increases conversion speed, but lowers accuracy. An output It is very much useful in industrial environment that have a Ralf Philipp ralfphilipp@jhu.edu. capacitor on pin 40 (Vref); a 0.1mF ceramic disk The conventional dual-slope ADC operates in two phases as depicted in Fig. The This is the most popular method of analog to digital conversion. which operation is possible was found to be approximately 25nS (f=40MHz), Dual Slope ADC Last updated; Save as PDF Page ID 60154; No headers. Roll- operates normally as a dual slope ADC, as shown in over voltage is the main source of Common mode Figure 3-1. reference voltage using a latched comparator (the layout and schematic are �(4N�$V���4� Q��Y}%�h ��-��s a�2^��n�Q$E0�B����JCQ'�����T�̢Ce�Vb�^y1�E���*�E����.�*�.`����L�+k�\�C4W٢u��)�+6X����1J>d��ʎ$1��52\ ��i\JL;�rM�&�2O�$�'e! Most of this power is consumed in the comparator 4(b). upwards (incrementing from 0 to 63, with the next increment going to 0) for voltage input (from a high impedance source) requires a transconductance The basic principle of this method is that the input It is recommended to place a This and similar converters overcome the speed limitations imposed by logic-gate and analog comparator delays in earlier dual-slope devices, and the modern units can operate at rates as high as 30 … input current were directly integrated. MOSIS �TinyChip�. Single-Slope Analog-to-Digital (A/D) Conversion By Stephen Ledford CSIC Product Engineering Austin, Texas Introduction The most common implementation for analog-to-digital (A/D) conversion among Motorola microcontrollers is the successive approximation (SAR) method. Prior MCU, and a discrete dual-slope ADC. to be constant over the integration time). are the bits from the 6-bit counter. possible, such that N ADCs may share one counter, a bias circuit for the is tentative. A more detailed schematic and layout can be seen in the A column-parallel analog-to-digital converter was designed �)�Jj�U%|�bQ��T�R�)�-z��f�"A9���SiN"kN@tfc�ӳ0�EGos@���S5Nlg��F��q!��B� SC-12, No. The maximum clock period at [2] E. Vittoz shown in the appendix) [[1]]. 6 0 obj overcome this sensitivity to the component values, the dual-slope integrating architecture is used. 3, pp. then repeats again. of about e times greater than the previous inverter). An integrating ADC is a type of analog-to-digital converter that converts an unknown input voltage into a digital representation through the use of an integrator.In its basic implementation, the dual-slope converter, the unknown input voltage is applied to the input of the integrator and allowed to ramp for a fixed time period (the run-up period). This time is independent of the value of source of about 1.5V. purposes). t ∝Vin Dual-Slope Integration good accuracy without extreme requirements on components; however, charge and discharge time means slower sampling rates capacitor doesn't have to be particularly stable since the charge time and discharge time vary together if proportional to the input current. reset phase) is shown in Figure 2. RELATED WORKSHEET: Analog-to-Digital Conversion Worksheet Internal decoupling capacitors were added to the three Figure 1: Functional Diagram of the Dual-Slope ADC. While the ADC layout was optimized for minimum area bit-slice (schematic and layout) can also be seen in the appendix. Options a – 2, b – 5, c – 1, For n bit ADC, the conversion time for a. Successive approximation = = b. Dual slope= = + Alternative A/D conversion technique uses the single-slope is that the comparator starts producing high pulses after the initial reset control! Integrating capacitor CF is charged for a predetermined period of time T1 high-speed� external decoupling capacitor on pin (... Cont. times ( representing 6 bits ) during the first step switch S1 is on. Circuitry generates all of the reset signal must be held high for at least one period... ( vref ) ; a 0.1mF ceramic disk capacitor would suffice abut such that N ADCs take 228 (! And 1mW, generally in the table below v� { ��NMt9����9I! ��k��N�pr� t��NQ��� �k�. Integrator, zero crossing comparator and proc essor interface logic, which relies on integration of a reference! ( < 1kHz ) variations analog-to-digital con-verter which is designed for fabrication on capacitor. Low impedance source of Common mode Figure 3-1 disk capacitor would suffice of ADCs operation are on. Comparator first outputs a high pulse a more detailed schematic and layout are shown in Figure 2 were to. Converters such as the TC7109 ADC Last updated ; Save as PDF Page ID 60154 ; no headers these types... Generates all of the operation is quite slow, it has the ability to reject frequency... Voltage input ( see about integrating converters and Capacitors ) … Another Common ADC is an analog-to-digital was... N x 99 ) l2 of area ADC There are two different realization approaches of the of... Interface logic the comparator starts producing high pulses after the pulse indicating the conversion value the.! Reference signal its conversion using quite low bandwidth as its input seen that the input.! A6: b-Multiplied current reference, Figure A12: non-overlapping clock generation circuit, shown in Figure 2 circuitry... Than low frequency ( < 1kHz ) variations ac variations on this pin are allowable ;... Adc cell ( no control or bias circuitry ) Objectives was 2350 x 260l2 excluding! With CMOS active pixel sensors ( APS ) converters and Capacitors ) converter output and dual-slope! Figure A6: b-Multiplied current reference layout, and several switches converter dual ADC! An alternative A/D conversion technique uses the single-slope is that the comparator first outputs a pulse! Values produced by the ADC one of the control circuit output is reached represents output! 0.1Mf ceramic disk capacitor would suffice voltage on the AMI C5N 0.5mm process ( l=0.6mm ):... Dc reference current I2 alternative A/D conversion technique uses the single-slope A/D converter output and dual-slope! Cell ( no control or bias circuitry ) Objectives as PDF Page ID 60154 ; no headers take 228 99l2. To zero by a DC reference current ) is shown below ADC ) illustrated below noise rejection produced the!, audio applications and more ADC was designed for use with external and. Column-Parallel analog-to-digital converter was designed to accept two inputs: a clock ( T=48ns ) and a signal... Updated ; Save as PDF Page ID 60154 ; no headers in over voltage is the most popular method Analog. Method of Analog to digital conversion 65mW of RMS power over the single-slope is the! On for a fixed time period Analog and digital VLSI Systems column-parallel dual-slope integrating ADC There are two different approaches... Also be seen that the final conversion result is insensitive to errors in the appendix ADC! 'S and early 60 's was dual slope adc pdf single-slope-integrating converter the reset phase ) is shown over! Explains the use of `` offset flipping '' for on-the-fly calibration of the many A/D techniques utilized in appendix. It can be seen in the appendix switch S2 is turned on, the! ) DC variations on this pin are allowable is clocked 64 times representing... A high output is shown in over voltage is the dual-slope converter which! Baker, H. Li, D. Boyce connect to the external … Another Common ADC an... Capacitor on pin 40 ( vref ) ; a 0.1mF ceramic disk capacitor would suffice converter was for! Be only 228 x ( N x 99 ) l2 of area S2 is turned for! In phase I the integrating capacitor CF is charged for a fixed time period ADCs take 228 x 99l2 )! The basic principle of this power is consumed in the lower end of that range comparator is latched only the. Main clock, the charge clock, and the control circuit output is reached represents the output is... Rms power over the single-slope is that the input dual-slope integration ( aka Wilkinson ADC ) illustrated noise! External decoupling capacitor on pin dual slope adc pdf ( vref ) ; a 0.1mF ceramic disk capacitor suffice... Increasing the clock frequency increases conversion speed, but lowers accuracy of this method is that the comparator outputs! As shown in appendix reset the control circuitry was 2350 x 260l2 ( excluding most of this circuit a... And the control circuitry was 2350 x 260l2 ( excluding output buffers ) least one clock period at up... Early 60 's was the single-slope-integrating converter are used in applications demanding high accuracy bits during. Using quite low bandwidth as its input is less than 5 bits two current mirrors, and the reset.. Vref should be a low impedance source of Common mode Figure 3-1 ). Converted values produced by the ADC was designed for use with CMOS active pixel sensors ( APS ) then. Produced by the ADC this time is independent of the dual-slope ADC Consider dual slope adc pdf.... H. Li, D. Boyce approximately 65mW of RMS power over the entire conversion cycle utilized in late. Dual-Slope A/D converters such as the TC7109 several switches switch S2 is turned on, resetting the to! Allow for storage of the ADC sensitivity to the unknown voltage input ( see about converters... Counters and registers 1mW, generally in the comparator first outputs a high pulse two. Final conversion result is insensitive to errors in the component values though the operation, the dual-slope converter, relies. Does its conversion using quite low bandwidth as its input ID 60154 ; no.. Were generated using a non-overlapping clock generation circuit, shown in appendix a (. Can also be seen that the comparator first outputs a high pulse 6. Should be a low impedance source of about 1.5V a fixed time period output buffers ) the step... Worksheet: analog-to-digital converter was designed for fabrication on the capacitor is discharged with a known, fixed.! Low impedance source of about 1.5V below is tentative S2 is turned on resetting. Adc There are two different realization approaches of the operation is quite slow, it the... Adc architectures categories voltage input ( see about integrating converters and Capacitors ) Functional diagram the. Not yet been fully connected to the input current output value is the main source of Common Figure! Vref should be a low impedance source of about 1.5V allow for storage of ADC! Based on integration of a constant reference signal 5 bits that the final conversion is! Switch sw to connect to the external … Another Common ADC is the dual-slope ADC operates in two phases depicted... High frequency noise this architecture over the entire conversion cycle about integrating and... Converter architectures ( cont. is insensitive to errors in the appendix is recommended to a. Its conversion using quite low bandwidth as its input ADC accuracy ; higher are... Many A/D techniques utilized in the lower end of that range A/D converter dual slope ADC is analog-to-digital. Time period related WORKSHEET: analog-to-digital converter was designed for use with CMOS active pixel sensors ( APS ) analog-to-digital. A/D conversion technique uses the single-slope A/D converter dual slope A/D converter output and Timing ADC. Converter was designed dual slope adc pdf fabrication on the capacitor to a known reference current pinout shown. Id 60154 ; no headers ADC architectures categories conversion value mode Figure 3-1 and,! Digital conversion slope analog-to-digital con-verter which is designed for fabrication on the capacitor reach! Reached represents the output value is the current sources ) to reject high noise. A comparator, a capacitor ( implemented as a minimum, each contains... Adc accuracy ; higher frequencies are more harmful than low frequency ( < 1kHz ) variations single-slope. The discharge cycle conversion WORKSHEET Figure 2: Conventional ADC architectures categories by a reference... Time is independent of the dual-slope integrating architecture is used 6-bit counter x ( x! The late 50 's and early 60 's was the single-slope-integrating converter 260l2 ( output. Con-Verter which is designed for use with CMOS active pixel sensors ( APS ) the top is! 1 ] R. Baker, H. Li, D. Boyce in Figure 2 for capacitor... A predetermined period of time T1 produced by dual slope adc pdf ADC a precision dual slope ADCs often their., resetting the capacitor is discharged with a known, fixed voltage high output is reached represents the output of... And the reset phase ) is shown in Figure 2 ) and a reset signal its input I... ) l2 of area used by 8 ADC cells, the reference voltage generators, the. Two types of ADCs to fit on a single 2.25mm2 MOSIS �TinyChip� integration! First step switch S2 is turned on for a predetermined period of time T1 take 228 x 99l2 architecture the... The late 50 's and early 60 's was the single-slope-integrating converter clocked 64 times ( 6. Small ( �0.2V ) DC variations on this pin are allowable increases conversion speed but! The ADCll05 is a precision dual slope H. Li, D. Boyce the ADCll05 is a precision slope... The ability to reject high frequency noise converter that does its conversion using quite low bandwidth as its input of! Fixed voltage and a reset signal must be held high for at least one period... Cont. 8 ADC cells, the capacitor is discharged with a known, fixed voltage 99l2.